Semiconductor device

ABSTRACT

A semiconductor device contains a semiconductor substrate, a cathode, an anode, and a gate electrode. The semiconductor device has a cathode segment disposed in a portion corresponding to at least the cathode, an anode segment disposed in a portion corresponding to the anode, a plurality of embedded segments disposed in a portion closer to the cathode segment than to the anode segment, a takeoff segment disposed between the gate electrode and the embedded segments to electrically connect the gate electrode to the embedded segments, and a channel segment disposed between the adjacent embedded segments.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Applications No. 2011-282028 filed on Dec. 22, 2011 andNo. 2012-272125 filed on Dec. 13, 2012, the contents all of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device containing ananode formed on one surface of a semiconductor part and a plurality ofcathode segments formed on the other surface of the semiconductor part,suitable for use in a static induction thyristor, a GTO thyristor, etc.

2. Description of the Related Art

In static induction thyristors, GTO thyristors, and the like, ingeneral, an anode is formed on a back surface of a silicon substrate,and a large number of cathode segments are disposed on a front surfaceof the silicon substrate. A gate region is disposed around the cathodesegments, and a gate electrode wiring is formed on the gate region (seeJapanese Laid-Open Patent Publication Nos. 2001-119014, H09-008280, and2000-058814).

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor devicecapable of exhibiting a reduced effective chip area and improved turn-onand turn-off switching speeds in the above static induction thyristors,GTO thyristors, and the like.

[1] According to a first aspect of the present invention, there isprovided a semiconductor device containing a first conductive typesemiconductor substrate, at least one cathode formed on one surface ofthe semiconductor substrate, an anode formed on the other surface of thesemiconductor substrate, and a gate electrode electrically insulatedfrom the cathode, formed on the one surface of the semiconductorsubstrate to control current conduction between the cathode and theanode, wherein the semiconductor device has a first conductive typecathode segment disposed in a portion corresponding to at least thecathode in the one surface of the semiconductor substrate, a secondconductive type anode segment disposed in a portion corresponding to theanode in the other surface of the semiconductor substrate, a pluralityof second conductive type embedded segments sandwiched between thecathode segment and the anode segment in the semiconductor substrate,disposed in a portion closer to the cathode segment than to the anodesegment, a second conductive type takeoff segment disposed between thegate electrode and the embedded segments to electrically connect thegate electrode to the embedded segments, and a first conductive typechannel segment disposed between the embedded segments adjacent to eachother.

[2] In the invention, the semiconductor device may contain a pluralityof the cathodes, the gate electrode may have a frame shape surroundingthe cathodes, and the takeoff segment may be disposed immediately belowthe gate electrode to electrically connect the gate electrode to theembedded segments.

[3] In the invention, the semiconductor device may have an epitaxiallayer containing the cathode segment, the embedded segments, and thetakeoff segment at the side of the one surface of the semiconductorsubstrate, and the epitaxial layer preferably has a thickness of atleast 0.5 μm and less than 13 μm.

[4] In the invention, the epitaxial layer preferably has a thickness of0.5 to 10 μm.

[5] In the invention, the epitaxial layer preferably has a thickness of1 to 10 μm.

[6] In the invention, the epitaxial layer preferably has a thickness of1 to 5 μm. [7] In the invention, the epitaxial layer particularlypreferably has a thickness of 1 to 2 μm.

[8] In the invention, the semiconductor substrate preferably has athickness of 440 μm or less.

[9] In the invention, the anode segment preferably has a thickness of0.02 to 1.0 μm.

By using the semiconductor device of the present invention in the staticinduction thyristors, GTO thyristors, and the like, the effective chiparea can be reduced, and the turn-on and turn-off switching speeds canbe improved.

The above and other objects, features, and advantages of the presentinvention will become more apparent from the following description whentaken in conjunction with the accompanying drawings in which a preferredembodiment of the present invention is shown by way of illustrativeexample.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a semiconductor device according to anembodiment of the present invention;

FIG. 2A is a cross-sectional view taken along the line II-II in FIG. 1;

FIG. 2B is a transparent perspective view of the section;

FIG. 3A is a cross-sectional view taken along the line in FIG. 1;

FIG. 3B is a transparent perspective view of the section (an insulatinglayer is not shown);

FIG. 4A is a cross-sectional view taken along the line IV-IV in FIG. 1;

FIG. 4B is a transparent perspective view of the section (an insulatinglayer is not shown); and

FIG. 5 is a circuit diagram of a high-voltage pulse generating circuitto which the semiconductor device is connected.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the semiconductor device of the present invention,usable in a normally-off embedded gate-type static induction thyristoror the like, will be described below with reference to FIGS. 1 to 5. Itshould be noted that, in this description, a numeric range of “A to B”includes both the numeric values A and B as the lower limit and upperlimit values.

As shown in FIG. 1, a semiconductor device 10 according to thisembodiment contains a first conductive type semiconductor substrate 12(see, e.g., FIGS. 2A and 2B), has an approximately track-like topsurface appearance, has an approximately rectangular element region 14at the center, and has a channel stop region 16 located on the outermostperiphery. Further, the semiconductor device 10 has a field limitingregion 18 located around the element region 14, i.e. between the elementregion 14 and the channel stop region 16.

The element region 14 will be mainly described below. As shown in FIGS.2A and 2B, the semiconductor device 10 contains the first conductivetype semiconductor substrate 12, one or more cathodes 20 (e.g.containing a metal) formed on one surface 12 a of the semiconductorsubstrate 12, at least one anode 22 (e.g. containing a metal) formed onthe other surface 12 b of the semiconductor substrate 12, and a gateelectrode 24 (e.g. containing a metal) formed on the one surface 12 a ofthe semiconductor substrate 12 as shown in FIG. 3A to control currentconduction between the cathodes 20 and the anode 22, the gate electrode24 being electrically insulated from the cathodes 20. In the example ofFIG. 1, the semiconductor device 10 contains four cathodes 20, and thegate electrode 24 has a frame shape surrounding the four cathodes 20.Thus, the gate electrode 24 extends between the adjacent cathodes 20 andbetween each cathode 20 and the field limiting region 18. Though onlytwo lines are shown in the field limiting region 18 in FIG. 1, five totwenty lines are practically formed in the field limiting region 18.

Furthermore, as shown in FIGS. 2A and 2B, in the semiconductor device10, first conductive type cathode segments 26 are disposed in portionscorresponding to at least the cathodes 20 in the one surface 12 a of thesemiconductor substrate 12, and a second conductive type anode segment28 is disposed in a portion corresponding to the anode 22 in the othersurface 12 b of the semiconductor substrate 12.

In addition, as shown in FIGS. 3A, 3B, 4A, and 4B, a plurality of secondconductive type embedded segments 30 are sandwiched between the cathodesegments 26 and the anode segment 28 in the semiconductor substrate 12.The embedded segments 30 are disposed in portions closer to the cathodesegment 26 than to the anode segment 28, and are electrically connectedto the gate electrode 24. The embedded segments 30 are at anapproximately constant arrangement pitch Pa (see FIG. 4A). Firstconductive type channel segments 31 are disposed between the adjacentembedded segments 30. The embedded segments 30 and the gate electrode 24are electrically connected by second conductive type takeoff segments 32disposed between the embedded segments 30 and the gate electrode 24.First insulating layers 34 are interposed between the gate electrode 24and the cathode segments 26, and second insulating layers 36 areinterposed between the gate electrode 24 and the cathodes 20.

In this embodiment, the semiconductor device 10 has an epitaxial layer38 formed by an epitaxial growth process. The epitaxial layer 38includes the embedded segments 30, the cathode segments 26, and thetakeoff segments 32, and further includes first conductive type segmentsbetween the embedded segments 30 and the cathode segments 26. In thiscase, the thickness to of the epitaxial layer 38 is 0.5 μm or more butless than 13 μm. In this embodiment, the thickness ta is preferably 0.5to 10 μm, more preferably 1 to 10 μm, further preferably 1 to 5 μm,particularly preferably 1 to 2 μm. For example, when the thickness ta ofthe epitaxial layer 38 is 13 μm, the arrangement pitch Pa of theembedded segments 30 is 23 μm. In contrast, when the thickness ta of theepitaxial layer 38 is 2 μm, the arrangement pitch Pa of the embeddedsegments 30 is 12 μm, which is advantageous for reducing the chip areaof the semiconductor device 10. When the epitaxial layer 38 has asmaller thickness ta, the one surface 12 a of the semiconductorsubstrate 12 (the upper surface of the epitaxial layer 38) can be asubstantially flat surface free from mesa portions, and the cathode 20can be formed closer to the gate electrode 24. Therefore, such a smallerthickness ta is advantageous for reducing the chip area of thesemiconductor device 10. Furthermore, in this embodiment, since themetal gate electrode 24 extends on a large number of the takeoffsegments 32 and is electrically connected to a plurality of the embeddedsegments 30 by the takeoff segments 32, the gate electrode 24 per se canbe utilized for forming a shunt structure of the embedded segments 30,and a control signal can be rapidly sent to the embedded segments 30.This leads to improvement in the switching speed of the semiconductordevice 10.

Materials of the components may be as follows. For example, thesemiconductor substrate 12 is an n-type silicon substrate having animpurity concentration of 10¹³ (cm⁻³) order, the cathode segment 26 isan n⁺ impurity region having an impurity concentration of 10¹⁹ (cm⁻³)order, the anode segment 28, each embedded segment 30, and each takeoffsegment 32 are a p⁺ region having an impurity concentration of 10¹⁹(cm⁻³) order, the first insulating layer 34 is an SiO₂ film, the secondinsulating layer 36 is an SiN_(x) film, a polyimide film, or a siliconefilm, and the cathode 20, the anode 22, and each gate electrode 24contain aluminum (Al).

The thickness tb of the semiconductor substrate 12 (see FIG. 3A) is lessthan 460 μm. In this embodiment, the thickness tb is preferably 440 μmor less, more preferably 260 to 440 μm, further preferably 300 to 430μm, particularly preferably 360 to 410 μm. As long as the thickness tbof the semiconductor substrate 12 is controlled within theabove-mentioned range, the on voltage can be lowered to reduce theturn-on loss, though the turn-off leakage current is not reduced.Therefore, the semiconductor device 10 can act to improve the turn-onefficiency in a practical circuit. In view of improving the deviceefficiency, the turn-on loss reduction has priority over the turn-offloss reduction. Thus, the device efficiency can be improved bycontrolling the thickness tb of the semiconductor substrate 12 withinthe above range.

The thickness tc of the anode segment 28 is less than 1.5 μm. In thisembodiment, the thickness tc is preferably 0.02 to 1.0 μm, furtherpreferably 0.05 to 0.5 μm, particularly preferably 0.1 to 0.2 μm. Whenthe thickness tc of the anode segment 28 is controlled within theabove-mentioned range, the turn-off leakage current can be reduced toreduce the turn-off loss, though the on voltage is not lowered.Therefore, the semiconductor device 10 can act to improve the turn-offefficiency in a practical circuit.

Particularly in this embodiment, since the thickness tb of thesemiconductor substrate 12 is less than 460 μm and the thickness tc ofthe anode segment 28 is less than 1.5 μm, both the turn-on and turn-offlosses can be reduced. Consequently, the semiconductor device 10 can actto improve both the turn-on and turn-off efficiencies in a practicalcircuit.

Evaluation of the turn-on switching speed, turn-off switching speed,turn-on efficiency, and turn-off efficiency of a practical circuit usingthe semiconductor device 10 of this embodiment will be described below.

As shown in FIG. 5, the turn-on switching speed, turn-off switchingspeed, turn-on efficiency, and turn-off efficiency are evaluated using ahigh-voltage pulse generating circuit shown in FIG. 1 of JapaneseLaid-Open Patent Publication No. 2004-072994.

As shown in FIG. 5, in the high-voltage pulse generating circuit 40, adirect-current power source unit 46 contains a direct-current powersource 42 and a capacitor 44 for reducing the high-frequency impedance.A coil 52, a first semiconductor switch 54, and a second semiconductorswitch 56 are series-connected to both ends 48, 50 of the direct-currentpower source unit 46. One end 58 of the coil 52 is connected to an anodeterminal A of the first semiconductor switch 54. A diode 62 isinterposed between the other end 60 of the coil 52 and a controlterminal (gate terminal) G of the first semiconductor switch 54 suchthat the anode is connected to the control terminal G. A load 64requiring a high-voltage pulse is connected in parallel with the coil52. The second semiconductor switch 56 contains a power metal-oxidesemiconductor field-effect transistor 68 (hereinafter referred to as thepower MOSFET 68) and a gate drive circuit 70. The power MOSFET 68 isequipped with an inverse-parallel-connected avalanche diode 66. The gatedrive circuit 70 is connected to a gate terminal G and a source terminalS of the power MOSFET 68 to control the on and off states of the powerMOSFET 68.

In the high-voltage pulse generating circuit 40, the semiconductordevice 10 of this embodiment is connected as the first semiconductorswitch 54, and a capacitor is connected as the load 64. An electricpower is supplied to the high-voltage pulse generating circuit 40, andthe semiconductor device 10 is turned on. After the elapse of apredetermined charging time, the semiconductor device 10 is turned off,and a high voltage is generated at both ends of the load.

The turn-on switching speed is evaluated in terms of a time elapseduntil the first semiconductor switch 54 (the semiconductor device 10) isturned on after an on signal (high-level signal) is output from the gatedrive circuit 70 to the gate terminal G of the power MOSFET 68 in thesecond semiconductor switch 56.

The turn-off switching speed is evaluated in terms of a time elapseduntil the first semiconductor switch 54 (the semiconductor device 10) iscompletely turned into the off state after an off signal (low-levelsignal) is output from the gate drive circuit 70 to the gate terminal Gof the power MOSFET 68 in the second semiconductor switch 56. Theturn-on efficiency is a ratio of an energy stored in the coil 52. Theenergy ratio is calculated from a current I_(L), which flows through thecoil 52 when the semiconductor device 10 is turned on. Thus, as the onvoltage is lowered (the turn-on loss is reduced), the energy stored inthe coil 52 is increased to improve the turn-on efficiency. On thecontrary, as the on voltage is increased (the turn-on loss isincreased), the energy stored in the coil 52 is reduced to lower theturn-on efficiency.

The turn-off efficiency is a maximum ratio, at which the energy storedin the coil 52 can be converted to an energy stored in the load(capacitor) 64. The maximum ratio is calculated from a highest voltage(highest generated voltage) V_(L), which is generated between both endsof the load 64 when the semiconductor device 10 is turned off. Thus, asthe turn-off leakage current is reduced (the turn-off loss is reduced),the highest generated voltage V_(L) is increased, so that the ratio ofthe conversion to the energy stored in the load (capacitor) 64 isincreased, resulting in improvement of the turn-off efficiency. On thecontrary, as the turn-off leakage current is increased (the turn-offloss is increased), the highest generated voltage V_(L) is lowered, sothat the ratio of the conversion to the energy stored in the load(capacitor) 64 is reduced to lower the turn-off efficiency.

FIRST EXAMPLE

In First Example, the semiconductor devices 10 of Examples 1 to 5 andReference Examples 1 and 2, which had various thicknesses ta of theepitaxial layers 38, were evaluated with respect to the arrangementpitch of the embedded segments 30, the turn-on switching speed (relativespeed), and the turn-off switching speed (relative speed).

EXAMPLE 1

The semiconductor device of Example 1 was produced such that thethickness tb of the semiconductor substrate 12 was 460 μm, the thicknesstc of the anode segment 28 was 1.5 μm, and the thickness ta of theepitaxial layer 38 was 10 μm in the semiconductor device 10 shown inFIGS. 1 to 4B.

EXAMPLES 2 to 5

The semiconductor devices of Examples 2, 3, 4, and 5 were produced inthe same manner as Example 1 except that the thicknesses ta of theepitaxial layers 38 were 5, 2, 1, and 0.5 μm, respectively.

REFERENCE EXAMPLES 1 AND 2

The semiconductor device of Reference Example 1 and 2 were produced inthe same manner as Example 1 except that the thickness ta of theepitaxial layer 38 were 13 and 0.1 μm respectively.

Evaluation

The arrangement pitch Pa of the embedded segments 30 was obtained by asimulation. In the simulation, the epitaxial layer 38 was grown to apredetermined thickness under such a condition that the channel segments31 had a constant width (constant distance between the adjacent embeddedsegments 30) of 2 μm.

The turn-on and turn-off switching speeds were evaluated using thehigh-voltage pulse generating circuit 40 shown in FIG. 5 (thehigh-voltage pulse generating circuit shown in FIG. 1 of JapaneseLaid-Open Patent Publication No. 2004-072994) as described above.

Thus, the turn-on switching speed was evaluated in terms of the timeelapsed until the first semiconductor switch 54 (the semiconductordevice 10) was turned on after the on signal (high-level signal) wasoutput from the gate drive circuit 70 to the gate terminal G of thepower MOSFET 68.

The turn-off switching speed was evaluated in terms of the time elapseduntil the first semiconductor switch 54 (the semiconductor device 10)was completely turned into the off state after the off signal (low-levelsignal) was output from the gate drive circuit 70 to the gate terminal Gof the power MOSFET 68.

The turn-on switching speed (the time elapsed until the semiconductordevice 10 was turned on after the on signal output) of Reference Example1 was represented by ton. The turn-on switching speeds of Examples 1 to5 and Reference Example 2 were evaluated relative to the speed ton.

Similarly, the turn-off switching speed (the time elapsed until thesemiconductor device 10 was completely turned into the off state afterthe off signal output) of Reference Example 1 was represented by toff.The turn-off switching speeds of Examples 1 to 5 and Reference Example 2were evaluated relative to the speed toff.

The evaluation results are shown in Table 1.

TABLE 1 Embedded Turn-on Turn-off Epitaxial segment switching switchinglayer arrangement speed speed thickness pitch (evaluated with (evaluatedwith (μm) (μm) time (s)) time (s)) Reference 13 23.0 ton toff Example 1Example 1 10 20.0 0.86 × ton 0.98 × toff Example 2 5 15.0 0.64 × ton0.96 × toff Example 3 2 12.0 0.50 × ton 0.94 × toff Example 4 1 11.00.46 × ton 0.93 × toff E Example 5 0.5 10.5 0.52 × ton 0.95 × toffReference 0.1 10.1 0.91 × ton 1.21 × toff Example 2

As shown in Table 1, in Examples 1 to 5, the embedded segments 30 had asmall arrangement pitch Pa, which was advantageous for reducing the chiparea. Furthermore, the turn-on and turn-off switching speeds of Examples1 to 5 were higher than those of Reference Example 1. In particular, theturn-on and turn-off switching speeds of Examples 3 and 4 weresignificantly increased. In Example 5, due to the smaller thickness taof the epitaxial layer 38, the conductivity of the embedded segments 30was lowered, whereby the switching speeds were lower than those ofExamples 3 and 4. In Reference Example 2, due to the further smallerthickness ta of the epitaxial layer 38, the conductivity of the embeddedsegments 30 was further lowered, whereby the turn-off switching speedwas lower than that of Reference Example 1.

Consequently, the thickness ta of the epitaxial layer 38 was preferably0.5 to 10 μm, more preferably 1 to 10 μm, further preferably 1 to 5 μm,particularly preferably 1 to 2 μm.

SECOND EXAMPLE

In Second Example, the semiconductor devices 10 of Examples 11 to 16 andReference Example 11, which had various thicknesses tb of thesemiconductor substrates 12, were evaluated with respect to the turn-onand turn-off efficiencies.

EXAMPLE 11

The semiconductor device of Example 11 was produced such that thethickness tb of the semiconductor substrate 12 was 440 μm, the thicknessto of the epitaxial layer 38 was 2 μm, and the thickness tc of the anodesegment 28 was 1.5 μm in the semiconductor device 10 shown in FIGS. 1 to4B.

EXAMPLES 12 TO 16

The semiconductor devices of Examples 12, 13, 14, 15, and 16 wereproduced in the same manner as Example 11 except that the thicknesses tbof the semiconductor substrates 12 were 430, 410, 360, 300, and 260 μm,respectively.

REFERENCE EXAMPLE 11

The semiconductor device of Reference Example 11 was produced in thesame manner as Example 11 except that the thickness tb of thesemiconductor substrate 12 was 200 μm.

Evaluation: Turn-On and Turn-Off Efficiencies

The turn-on and turn-off efficiencies were evaluated using thehigh-voltage pulse generating circuit 40 shown in FIG. 5 (thehigh-voltage pulse generating circuit shown in FIG. 1 of JapaneseLaid-Open Patent Publication No. 2004-072994) as described above. In thehigh-voltage pulse generating circuit 40, the semiconductor device 10was connected as the first semiconductor switch 54, and the capacitorwas connected as the load 64. The electric power was supplied to thehigh-voltage pulse generating circuit 40, and the semiconductor device10 was turned on. After the elapse of the predetermined charging time (4μs), the semiconductor device 10 was turned off, and the high voltagewas generated at both ends of the load.

The turn-on efficiency was evaluated in terms of the ratio of the energystored in the coil 52. The energy ratio was calculated from the current,which flowed through the coil 52 when the semiconductor device 10 wasturned on. Specifically, the energy ratio was obtained using theexpression of (I/Io)×100 (%), in which Io (A) represented a currentobtained in an optimum structure, and I (A) represented a current thatpractically flowed through the coil 52 when the semiconductor device 10was turned on.

The turn-off efficiency was evaluated in terms of the maximum ratio, atwhich the energy stored in the coil 52 could be converted to the energystored in the load (capacitor) 64. Specifically, the maximum ratio wasobtained using the expression of (V/Vo)×100 (%), in which Vo (V)represented a highest generated voltage obtained in an optimumstructure, and V (V) represented a highest voltage (highest generatedvoltage) practically generated between both ends of the load when thesemiconductor device 10 was turned off.

The evaluation results are shown in Table 2.

TABLE 2 Semiconductor Turn-on Turn-off substrate thickness efficiencyefficiency (μm) (%) (%) Example 11 440 83 76 Example 12 430 84 72Example 13 410 85 68 Example 14 360 89 58 Example 15 300 91 43 Example16 260 94 33 Reference 200 97 21 Example 11

As shown in Table 2, in Examples 11 to 16, the turn-on efficiencies wereat least 83% to achieve high device efficiencies. As the thickness tb ofthe semiconductor substrate 12 was reduced, the turn-off efficiency waslowered. However, even in Example 16, the turn-off efficiency was 33%,which was at a practical level (30% or more). In Reference Example 11,the turn-on efficiency was a high value of 97%, while the turn-offefficiency was 21% below the practical level.

Consequently, the thickness tb of the semiconductor substrate 12 wasdesirably less than 460 μm, preferably 440 μm or less, more preferably260 to 440 μm, further preferably 300 to 430 μm, particularly preferably360 to 410 μm.

THIRD EXAMPLE

In Third Example, the semiconductor devices 10 of Examples 17 to 22,which had various thicknesses tc of the anode segments 28, wereevaluated with respect to the turn-on and turn-off efficiencies.

EXAMPLE 17

The semiconductor device of Example 17 was produced such that thethickness tb of the semiconductor substrate 12 was 460 μm, the thicknessta of the epitaxial layer 38 was 2 μm, and the thickness tc of the anodesegment 28 was 1.0 μm in the semiconductor device 10 shown in FIGS. 1 to4B.

EXAMPLES 18 TO 22

The semiconductor devices of Examples 18, 19, 20, 21, and 22 wereproduced in the same manner as Example 17 except that the thickness tcof the anode segment 28 was 0.5, 0.2, 0.1, 0.05, or 0.02 μmrespectively.

Evaluation: Turn-On and Turn-Off Efficiencies

The turn-on and turn-off efficiencies were evaluated in the same manneras Second Example, and the duplicate explanations thereof are omitted.

The evaluation results are shown in Table 3.

TABLE 3 Anode segment Turn-on Turn-off thickness efficiency efficiency(μm) (%) (%) Example 1.0 82 81 17 Example 0.5 81 81 18 Example 0.2 79 8219 Example 0.1 79 82 20 Example 0.05 78 82 21 Example 0.02 77 83 22

As shown in Table 3, in Examples 17 to 22, the turn-off efficiencieswere at least 81%. As the thickness tc of the anode segment 28 wasreduced, the turn-on efficiency was lowered. However, even in Example22, the turn-on efficiency was 77%, which was at a practical level (70%or more).

Consequently, the thickness tc of the anode segment 28 was desirablyless than 1.5 pm, preferably 0.02 to 1.0 μm, further preferably 0.05 to0.5 μm, particularly preferably 0.1 to 0.2 μm.

FOURTH EXAMPLE

In Fourth Example, the semiconductor devices 10 of Examples 31 to 48,which had various thicknesses tb of the semiconductor substrates 12 andvarious thicknesses tc of the anode segments 28, were evaluated withrespect to the turn-on and turn-off efficiencies.

EXAMPLE 31

The semiconductor device of Example 31 was produced such that thethickness tb of the semiconductor substrate 12 was 440 μm, the thicknessta of the epitaxial layer 38 was 2 μm, and the thickness tc of the anodesegment 28 was 0.2 μm in the semiconductor device 10 shown in FIGS. 1 to4B.

EXAMPLES 32 AND 33

The semiconductor devices of Examples 32 and 33 were produced in thesame manner as Example 31 except that the thicknesses tc of the anodesegments 28 were 0.1 and 0.05 μm, respectively.

EXAMPLE 34

The semiconductor device of Example 34 was produced in the same manneras Example 31 except that the thickness tb of the semiconductorsubstrate 12 was 430 μm.

EXAMPLES 35 AND 36

The semiconductor devices of Examples 35 and 36 were produced in thesame manner as Example 34 except that the thicknesses tc of the anodesegments 28 were 0.1 and 0.05 μm, respectively.

EXAMPLE 37

The semiconductor device of Example 37 was produced in the same manneras Example 31 except that the thickness tb of the semiconductorsubstrate 12 was 410 μm.

EXAMPLES 38 AND 39

The semiconductor devices of Examples 38 and 39 were produced in thesame manner as Example 37 except that the thicknesses tc of the anodesegments 28 were 0.1 and 0.05 μm, respectively.

EXAMPLE 40

The semiconductor device of Example 40 was produced in the same manneras Example 31 except that the thickness tb of the semiconductorsubstrate 12 was 360 μm.

EXAMPLES 41 AND 42

The semiconductor devices of Examples 41 and 42 were produced in thesame manner as Example 40 except that the thicknesses tc of the anodesegments 28 were 0.1 and 0.05 μm, respectively.

EXAMPLE 43

The semiconductor device of Example 43 was produced in the same manneras Example 31 except that the thickness tb of the semiconductorsubstrate 12 was 300 μm.

EXAMPLES 44 AND 45

The semiconductor devices of Examples 44 and 45 were produced in thesame manner as Example 43 except that the thicknesses tc of the anodesegments 28 were 0.1 and 0.05 μm, respectively.

EXAMPLE 46

The semiconductor device of Example 46 was produced in the same manneras Example 31 except that the thickness tb of the semiconductorsubstrate 12 was 260 μm.

EXAMPLES 47 AND 48

The semiconductor devices of Examples 47 and 48 were produced in thesame manner as Example 46 except that the thicknesses tc of the anodesegments 28 ere 0.1 and 0.05 μm respectively.

Evaluation: Turn-On and Turn-Off Efficiencies

The turn-on and turn-off efficiencies were evaluated in the same manneras Second Example, and the duplicate explanations thereof are omitted.

The evaluation results are shown in Table 4.

TABLE 4 Semiconductor Anode substrate segment Turn-on Turn-off thicknessthickness efficiency efficiency (μm) (μm) (%) (%) Example 31 440 0.2 8179 Example 440 0.1 81 79 Ex. 33 440 0.05 81 79 Ex. 34 430 0.2 82 77 Ex.35 430 0.1 82 77 Ex. 36 430 0.05 82 77 Ex. 37 410 0.2 82 75 Ex. 38 4100.1 82 75 Ex. 39 410 0.05 82 75 Ex. 40 360 0.2 84 70 Ex. 41 360 0.1 8470 Ex. 42 360 0.05 84 70 Ex. 43 300 0.2 85 63 Ex. 44 300 0.1 85 63 Ex.45 300 0.05 84 63 Ex. 46 260 0.2 87 58 Ex. 47 260 0.1 86 58 Ex. 48 2600.05 86 58

As shown in Table 4, in Examples 31 to 48, the turn-on efficiencies wereat least 81%, resulting in high device efficiencies. As the thickness tbof the semiconductor substrate 12 was reduced, the turn-off efficiencywas lowered. In Example 16 (in which the thickness tb of thesemiconductor substrate 12 was 260 μm), the turn-off efficiency was only33%. In contrast, in Examples 46 to 48, though the thickness tb of thesemiconductor substrate 12 was 260 μm, the turn-off efficiency wasincreased to 58%. It was considered that the increase was achieved byreducing the thickness tc of the anode segment 28.

It is to be understood that the semiconductor device of the presentinvention is not limited to the above embodiment, and various changesand modifications may be made therein without departing from the scopeof the invention.

What is claimed is:
 1. A semiconductor device comprising a firstconductive type semiconductor substrate, at least one cathode formed onone surface of the semiconductor substrate, an anode formed on the othersurface of the semiconductor substrate, and a gate electrode formed onthe one surface of the semiconductor substrate to control currentconduction between the cathode and the anode, the gate electrode beingelectrically insulated from the cathode, wherein the semiconductordevice has a first conductive type cathode segment disposed in a portioncorresponding to at least the cathode in the one surface of thesemiconductor substrate, a second conductive type anode segment disposedin a portion corresponding to the anode in the other surface of thesemiconductor substrate, a plurality of second conductive type embeddedsegments sandwiched between the cathode segment and the anode segment inthe semiconductor substrate, disposed in a portion closer to the cathodesegment than to the anode segment, a second conductive type takeoffsegment disposed between the gate electrode and the embedded segments toelectrically connect the gate electrode to the embedded segments, and afirst conductive type channel segment disposed between the adjacentembedded segments adjacent to each other.
 2. The semiconductor deviceaccording to claim 1, comprising a plurality of the cathodes, whereinthe gate electrode has a frame shape surrounding the cathodes, and thetakeoff segment is disposed immediately below the gate electrode toelectrically connect the gate electrode to the embedded segments.
 3. Thesemiconductor device according to claim 1, wherein the semiconductordevice has an epitaxial layer containing the cathode segment, theembedded segments, and the takeoff segment at a side of the one surfaceof the semiconductor substrate, and the epitaxial layer has a thicknessof at least 0.5 μm and less than 13 μm.
 4. The semiconductor deviceaccording to claim 3, wherein the epitaxial layer has a thickness of 0.5to 10 μm.
 5. The semiconductor device according to claim 4, wherein theepitaxial layer has a thickness of 1 to 10 μm.
 6. The semiconductordevice according to claim 5, wherein the epitaxial layer has a thicknessof 1 to 5 μm.
 7. The semiconductor device according to claim 6, whereinthe epitaxial layer has a thickness of 1 to 2 μm.
 8. The semiconductordevice according to claim 1, wherein the semiconductor substrate has athickness of 440 μm or less.
 9. The semiconductor device according toclaim 1, wherein the anode segment has a thickness of 0.02 to 1.0 μm.